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fremont micro devices FT25C64A ds spi serial eeprom 64k (8-bit wide) features ? serial peripheral interface (spi) compatible ? supports spi modes 0 (0,0) and 3 (1,1) ? data sheet describes mode 0 operation ? low voltage and low power operations ? FT25C64A v cc = 1.8v to 5.5v ? 20mhz clock rate (5v) ? maximum standby current < 1a (typically 0.02a and 0.06a @ 1.8v and 5.5v respectively) ? partial page write operation allo wed (32 bytes page write mode) ? self-timed programming cycle (5 ms max) ? block write protection (protect 1/4, 1/2, or entire array) ? write protect pin for hardware data protection ? high reliability: typically 1,000,000 cycles endurance ? 100 years data retention ? industrial temperature range (-40 to 85 ) ? standard 8-pin dip/sop/tssop pb-free packages description the FT25C64A is 65536 bits of serial electrical erasable and programmable read only memory, commonly known as eeprom. they are organized as 8192 words of 8 bits (1 byte) each. the devices are fabricated with proprietary advanced cmos process for low power and low voltage applications. these devices are available in standard 8-lead dip, 8-lead sop and 8-lead tssop packages. the memory is accessed via a simple serial peripheral interface (spi) compatible serial bus. the hold pin may be used to suspend any serial communication without resetting the serial sequence. while the device is paused, transitions on its input s will be ignored. our extended v cc range (1.8v to 5.5v) devices enables wide spectrum of applications. ? 2013 fremont micro devices inc. confidential rev 0.80 ds25c64a - page1
fremont micro devices FT25C64A ds pin configuration pin name pin function pin name pin function cs chip select gnd ground scl serial clock input vcc power supply si serial data input wp write protest so serial data output hold suspends serial input all these packaging types come in c onventional or pb-free certified. v c c s c l s o g n d FT25C64A 1 2 3 4 8 7 6 5 8l dip 8l sop 8l tssop s i p w s c d l o h figure 1: packaging types absolute maximum ratings industrial operating temperature???????????????????????????-40 to 85 storage temperature???????????????????????????????.-50 to 125 input voltage on any pin relative to ground????????????????????-0.3v to v cc + 0.3v maximum voltage??????????????????????????????????????8v esd protection on all pins????????????????????????????????>2000v * stresses exceed those listed under ?absolute maximum rating? may cause permanent damage to the device. functional operation of the device at conditions beyond those listed in the specification is not guaranteed. prolonged expo sure to extreme conditions m ay affect device reliability or functionality. ? 2013 fremont micro devices inc. confidential rev 0.80 ds25c64a-page2
fremont micro devices FT25C64A ds block diagram memory array status register address decoder data register output buffer mode decode logic clock generator si cs wp sck hold so vcc gnd figure 2: block diagram ? 2013 fremont micro devices inc. confidential rev 0.80 ds25c64a-page3
fremont micro devices FT25C64A ds pin descriptions (a) chip select ( cs ) the FT25C64A is selected when the cs pin is low. when the device is not selected, data will not be accepted via the si pin, and the serial output pin (so) will remain in a high impedance state. (b) serial input (si) the si pin is used to transfer data into the device. it receives instructions, addresses, and data. data is latched on the rising edge of the serial clock. (c)serial output (so) the so pin is used to transfer data out of the FT25C64A . during a read cycle, data is shifted out on this pin after the falling edge of the serial clock. (d) serial clock (sck) the sck is used to synchronize the communicati on between a master and the FT25C64A. instructions, addresses, or data present on the si pin are latched on the rising edge of the clock input, while data on the so pin is updated after the falling edge of the clock input. (e) write protect ( wp ) this pin is used in conjunction with the wpen bit in t he status register to prohibit writes to the non-volatile bits in the status register. when wp is low and wpen is high, writing to the non-volatile bits in the status register is disabled. all other o perations function normally. when wp is high, all functions, including writes to the non-volatile bits in the status r egister operate normally. if the wpen bit is set, wp low during a status register write sequence will disable writing to the status register. if an internal write cycle has already begun, wp going low will have no effect on the write. the wp pin function is blocked when the wpen bit in the status register is low. this allows the user to install the FT25C64A in a system with wp pin grounded and still be able to write to the status register. the wp pin functions will be enabled when the wpen bit is set high. (f) hold ( hold ) the hold pin is used in conjunction with the cs pin to select the ft 25c64a. when the device is selected and a serial sequence is underway, hold can be used to pause the serial communication with the master device without resetting the serial sequence. to pause, the hold pin must be brought low while the sck pin is low. to resume serial communication, the hold pin is brought high while the sck pin is low (sck may still toggle during hold ). inputs to the si pin will be ignored while the so pin is in the high impedance state. memory organization the FT25C64A devices have 256 pages respectively . since each page has 32 bytes, random word addressing to FT25C64A will require 13 bi ts data word addresses respectively. ? 2013 fremont micro devices inc. confidential rev 0.80 ds25c64a-page4
fremont micro devices FT25C64A ds device operation the FT25C64A utilizes an 8-bit instruction register. t he list of instructions and their operation codes are contained in table a. all instructions, addresses, and da ta are transferred with the msb first and start with a high-to-low cs transition. table a instruction set for the FT25C64A instruction name instruction format operation wren 0000 x110 set write enable latch wrdi 0000 x100 reset write enable latch rdsr 0000 x101 read status register wrsr 0000 x001 write status register read 0000 x011 read data from memory array write 0000 x010 write data to memory array (a) status register operation table b status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit2 bit 1 bit 0 wpen x x x bp1 bp0 wen rdy write enable (wren): the device will power up in the write disable state when vcc is applied. all programming instructions must therefore be preceded by a write enable instruction. write disable (wrdi): to protect the device against inadvertent writes, the write disable instruction disables all programming modes. the wrdi instru ction is independent of the status of the wp pin. read status register (rdsr): the read status register instruct ion provides access to the status register. the ready/busy and write enable status of the device can be determined by the rdsr instruction. similarly, the block writ e protection bits indicate the extent of protection employed. these bits are set by using the wrsr instruction. table c status register bit definition bit definition bit 0 ( rdy ) bit 0 = ?0? ( rdy ) indicates the device is ready. bit 0 = ?1? indicates the write cycle is in progress. bit 1 (wen) bit 1= ?0? indicates the device is not write enabled. bit 1 = ?1? indicates the device is write enabled. bit 2 (bp0) see table d. bit 3 (bp1) see table d. bits 4-6 are ?0?s when device is not in an internal write cycle. bit 7 (wpen) see table e. bits 0-7 are ?1? during an internal write cycle. ? 2013 fremont micro devices inc. confidential rev 0.80 ds25c64a-page5
fremont micro devices FT25C64A ds write status register (wrsr): the wrsr instruction allows the user to select one of four levels of protection. the FT25C64A is divided into four array se gments. one-quarter, one-half, or all of the memory segments can be protected. any of the data within an y selected segment will therefore be read only. the block write protection levels and corres ponding status register control bits are shown in table d. the three bits bp0, bp1, and wpen are nonvolatile cells that have the same properties and functions as the regular memory cells. table d block write protect bits status register bits level bp1 bp0 array address protected 0 0 0 none 1(1/4) 0 1 1800-1fff 2(1/2) 1 0 1000-1fff 3(all) 1 1 0000-1fff the wrsr instruction also allows the user to enable or disable the write protect ( wp ) pin through the use of the write protect enable (wpen) bit. hardwa re write protection is enabled when the wp pin is low and the wpen bit is ?1?. hardware write protection is disabled when either the wp pin is high or the wpen bit is ?0?. when the device is hardware write protect ed, writes to the status register, including the block protect bits and the wpen bit, and the block-protected sections in the memory array are disabled. writes are only allowed to sections of the memory that are not block-protected. note: when the wpen bit is hardware write protected, it cannot be changed back to ?0? as long as the wp pin is held low. table e wpen operation wpen wp wen protected blocks unprotected blocks status register 0 x 0 protected protected protected 0 x 1 protected writeable writeable 1 low 0 protected protected protected 1 low 1 protected writeable protected x high 0 protected protected protected x high 1 protected writeable writeable (b) eeprom operation read sequence (read): reading the FT25C64A via the serial output (so) pin requires the following sequence. after the cs line is pulled low to select a device, the read op-code is transmitted via the si line followed by the byte address to be read (a15 ? a0, see table f). upon completion, any data on the si line will be ignored. the data (d7 ? d0) at the specified address is then shif ted out onto the so line. if only one byte is to be read, the cs line should be driven high after the data comes out. the read sequence can be continued since the byte address is automatically in cremented and data will continue to be shifted out. when the highest address is reached, the addres s counter will roll over to the lowest address (0000h), allowing the entire memory to be read in one continuous read cycle. ? 2013 fremont micro devices inc. confidential rev 0.80 ds25c64a-page6
fremont micro devices FT25C64A ds write sequence (write): in order to program the FT25C64A, two separate instructions must be executed. first, the device must be write enabled vi a the wren instruction. then a write (write) instruction may be executed. also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. during an internal write cycle, all commands will be igno red except the rdsr instruction. a write instruction requires the following sequence. after the cs line is pulled low to select the device, the write op-code is transmitted via the si line followed by the byte address (a15 ? a0) and the data (d7?d0) to be programmed (see table f). programming will start after the cs pin is brought high. the low-to-high transition of the cs pin must occur during the sck low-time immediately after clocking in the d0 (lsb) data bit. the FT25C64A is capable of a 32-byte page write opera tion. after each byte of data is received, the five low-order address bits are internally incremented by one; the high order bits of the address will remain constant. if more than 32 bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. t he FT25C64A is automatica lly returned to the writ e disable state at the completion of a write cycle. note: if the device is not write enabled (wren), the device will ignore the write instruction and will return to the standby state, when cs is brought high. a new cs falling edge is required to reinitiate the serial communication. the ready/busy status of the device can be determi ned by initiating a read st atus register (rdsr) instruction. if bit 0 = ?1?, the write cycle is still in progress. if bit 0 = ?0?, the write cycle has ended. only the rdsr instruction is enabled during the write programming cycle. table f address key address FT25C64A a n a 12 -a 0 don?t care bits a 15 -a 13 ? 2013 fremont micro devices inc. confidential rev 0.80 ds25c64a-page7
fremont micro devices FT25C64A ds scl so d l o h t hdn t hds t hz t lz t hdn t hds cs figure 3: hold timing s c s c l s i s o hi-z hi-z t css t wh t wl t csh t cs t su t h valid in t v t ho t dis v ih v il v ih v il v ih v il v oh v ol figure 4: synchronous data timing (for mode 0) wren inst s c l s i s o hi-z s c figure 5: wren timing ? 2013 fremont micro devices inc. confidential rev 0.80 ds25c64a-page8
fremont micro devices FT25C64A ds wrdi inst s c l s i s o hi-z s c figure 6: wrdi timing rdsr inst cs scl si so hi-z 0 1 7 6 5 4 3 2 1 0 2 3 4 5 6 7 8 9 msb 10 11 12 13 14 15 figure 7: rdsr timing wrsr inst cs scl si so hi-z 0 1 7 3 2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data in figure 8: wrsr timing read inst cs scl si so hi-z 0 1 7 6 5 4 3 2 1 0 2 3 4 5 6 7 8 9 msb 22 23 24 25 26 27 28 29 30 31 15 14 1 0 data out byte address figure 9: read timing ? 2013 fremont micro devices inc. confidential rev 0.80 ds25c64a-page9
fremont micro devices FT25C64A ds write inst s c l s i s o hi-z 0 1 2 3 4 5 6 7 8 9 22 23 24 25 26 27 28 29 30 31 15 14 1 0 7 6 5 4 3 2 1 0 data in byte address s c figure 10: write timing ac characteristics applicable over recommended operating range from: t ai =-40 to +85 v cc = as specified, c l = 1 ttl gate and 30 pf (unless otherwise noted) FT25C64A 1.8-2.7 v 2.7-4.5 v 4.5-5.5 v symbol parameter min max min max min max unit f sck clock frequency, sck 5 10 20 mhz t ri input rise time 2 2 2 s t fi input fall time 2 2 2 s t wh sck high time 80 40 20 ns t wl sck low time 80 40 20 ns t cs cs high time 100 50 25 ns t css cs setup time 100 50 25 ns t csh cs hold time 100 50 25 ns t su data in setup time 20 10 5 ns t h data in hold time 20 10 5 ns t hd hold setup time 20 10 5 ns t cd hold hold time 20 10 5 ns t v output valid 0 80 0 40 0 20 ns t ho output hold time 0 0 0 ns t lz hold to output low z 0 100 0 50 0 25 ns t hz hold to output high z 200 80 40 ns t dis output disable time 200 80 40 ns t wc write cycle time 5 5 5 ms ? 2013 fremont micro devices inc. confidential rev 0.80 ds25c64a-page10
fremont micro devices FT25C64A ds dc characteristics applicable over recommended operating range from:t ai =-40 to +85 v cc = +1.8v to +5.5v(unless otherwise noted) symbol parameter test conditions min typi cal max unit v cc1 supply voltage 1.8 5.5 v v cc2 supply voltage 2.7 5.5 v v cc3 supply voltage 4.5 5.5 v i cc1 supply current v cc =5.0v @ 20mhz, so=open, read 7.5 10.0 ma i cc2 supply current v cc =5.0v @ 20mhz, so=open, read, write 4.0 10.0 ma i cc3 supply current v cc =5.0v @ 5mhz, so=open, read, write 4.0 6.0 ma i sb1 standby current v cc = 1.8v, cs = v cc 1.0 a i sb2 standby current v cc = 2.7v, cs = v cc 1.0 a i sb3 standby current v cc = 5.0v, cs = v cc 0.07 1.0 a i il input leakage v in = v cc or v ss 3.0 a i ol output leakage v in = v cc or v ss 3.0 a v il (1) input low level -0.6 v cc ? 0.3 v v ih(1) input high level v cc ? 0.7 v cc ? 0.5 v v ol1 output low level 3.6v ? v cc ? 5.5v, i ol = 3.0ma 0.4 v v oh1 output high level 3.6v ? v cc ? 5.5v, i oh =-1.6ma v cc ????? v ol2 output low level 1.8v ? v cc ? 3.6v, i ol = 0.15ma 0.2 v v oh2 output high level 1.8v ? v cc ? 3.6v, i oh =-100ua v cc ????? notes:1. v il min and v ih max are reference only and are not tested. ? 2013 fremont micro devices inc. confidential rev 0.80 ds25c64a-page11
fremont micro devices FT25C64A ds ordering information: FT25C64A - x x ? 2013 fremont micro devices inc. confidential rev 0.80 ds25c64a-page12 x - x circuit type t emp. range u: -40 -85 package d: dip8 s: sop8 t: tssop8 packaging b: tube t: tape and reel hsf r: ro hs g: green density package temperature range vcc hsf packaging ordering code rohs tube FT25C64A-udr-b dip8 -40 -85 1.8v-5.5v green tube FT25C64A-udg-b tube FT25C64A-usr-b rohs tape and reel FT25C64A-usr-t tube FT25C64A-usg-b sop8 -40 -85 1.8v-5.5v green tape and reel FT25C64A-usg-t tube FT25C64A-utr-b rohs tape and reel FT25C64A-utr-t tube FT25C64A-utg-b 64kbits tssop8 -40 -85 1.8v-5.5v green tape and reel FT25C64A-utg-t
fremont micro devices FT25C64A ds dip8 package outline dimensions dimensions in millimeters dimensions in inches symbol min max min max a 3.710 4.310 0.146 0.170 a1 0.510 0.020 a2 3.200 3.600 0.126 0.142 b 0.380 0.570 0.015 0.022 b1 1.524bsc 0.060 bsc c 0.204 0.360 0.008 0.014 d 9.000 9.400 0.354 0.370 e 6.200 6.600 0.244 0.260 e1 7.320 7.920 0.288 0.312 e 2.540 (bsc) 0.100 bsc l 3.000 3.600 0.118 0.142 e2 8.400 9.000 0.331 0.354 ? 2013 fremont micro devices inc. confidential rev 0.80 ds25c64a-page13
fremont micro devices FT25C64A ds sop8 package outline dimensions dimensions in millimeters dimensions in inches symbol min max min max a 1.350 1.750 0.053 0.069 a1 0.100 0.250 0.004 0.010 a2 1.350 1.550 0.053 0.061 b 0.330 0.510 0.013 0.020 c 0.170 0.250 0.006 0.010 d 4.700 5.100 0.185 0.200 e 3.800 4.000 0.150 0.157 e1 5.800 6.200 0.228 0.244 e 1.270 (bsc) 0.050 (bsc) l 0.400 1.270 0.016 0.050 0 8 0 8 ? 2013 fremont micro devices inc. confidential rev 0.80 ds25c64a-page14
fremont micro devices FT25C64A ds tssop8 package outline dimensions dimensions in millimeters dimensions in inches symbol min max min max d 2.900 3.100 0.114 0.122 e 4.300 4.500 0.169 0.177 b 0.190 0.300 0.007 0.012 c 0.090 0.200 0.004 0.008 e1 6.250 6.550 0.246 0.258 a 1.100 0.043 a2 0.800 1.000 0.031 0.039 a1 0.020 0.150 0.001 0.006 e 0.65 (bsc) 0.026 (bsc) l 0.500 0.700 0.020 0.028 h 0.25 (typ) 0.01 (typ) 1 7 1 7 ? 2013 fremont micro devices inc. confidential rev 0.80 ds25c64a-page15
fremont micro devices FT25C64A ds ? 2013 fremont micro devices inc. confidential rev 0.80 ds25c64a-page16 fremont micro devices (sz) limited #5-8, 10/f, changhong building, ke-ji nan 12 ro ad, nanshan district, shenzhen, guangdong 518057 tel: (86 755) 86117811 fax: (86 755) 86117810 fremont micro devices (hong kong) limited #16, 16/f, blk b, veristrong industrial centre, 34- 36 au pui wan street, fotan, shatin, hong kong tel: (852) 27811186 fax: (852) 27811144 fremont micro devices (usa), inc. 42982 osgood road fremont, ca 94539 tel: (1-510) 668-1321 fax: (1-510) 226-9918 web site: http://www.fremontmicro.com/ * information furnished is believed to be accurate and reliable. however, fremont micro devices, incorporated (bvi) assumes no responsibility for the c onsequences of use of such information or for any infringement of patents of other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent rights of fremont micro devices, incorporated (bvi). specifications mentioned in this publication ar e subject to change without notice. this publication supersedes and replaces all information previously supplied. fremont micro devices, incorporated (bvi) products are not authorized for use as critical com ponents in life support devices or systems without express written approval of fremont micro devices, incorporated (bvi ). the fmd logo is a registered trademark of fremont micro devices, incorporated (bvi). all other names ar e the property of their respective owners.

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